The present invention relates to a flash memory device, and more specifically, to a page buffer circuit of a flash memory device.
In general, a flash memory device includes a page buffer circuit for programming or reading a large quantity of data within a short period of time. The program operation or the read operation of the flash memory device is executed on a page basis by the page buffer circuit.
FIG. 1 is a circuit diagram showing a page buffer circuit and a Y-gate circuit of a conventional flash memory device.
A page buffer circuit 11 includes a plurality of page buffers. A Y-gate circuit 12 includes a plurality of Y-gates. Page buffers 20, 30 of the page buffer circuit 11 and Y-gates G1, G2 of the Y-gate circuit 12 are shown in FIG. 1 for simplicity. The page buffers 20, 30 are connected to a pair of bit lines, respectively. To be more specific, the page buffer 20 is connected between bit lines BLe1, BLo1 and the Y-gates G1. The page buffer 30 is connected between bit lines BLe2, BLo2 and the Y-gates G2. The Y-gates G1, G2 are further connected to a data I/O line DIOL.
The page buffer 20 includes a bit line select circuit 21 and a register circuit 22. The bit line select circuit 21 includes NMOS transistors N21 to N24. The register circuit 22 includes a precharge circuit P21, a sensing circuit 23, a latch circuit 24, switches N25, N26, and a reset circuit N27. The sensing circuit 23 includes NMOS transistors N28, N29. The page buffer 30 includes a bit line select circuit 31 and a register circuit 32. The bit line select circuit 31 includes NMOS transistors N31 to N34. The register circuit 32 includes a precharge circuit P31, a sensing circuit 33, a latch circuit 34, switches N35, N36, and a reset circuit N37. The sensing circuit 33 includes NMOS transistors N38, N39.
In the read operation or the program operation, the bit line select circuit 21 connects one of the bit lines BLe1, BLo1 to a sensing node SO1. Furthermore, the register circuit 22 senses read data from one of the bit lines BLe1, BLo1 connected to the sensing node SO1 and stores the sensing data therein. In addition, the register circuit 22 stores program data therein, which will be programmed into a memory cell connected to one of the bit lines BLe1, BLo1. As a result, the read data are transferred to the register circuit 22 through the sensing node SO1 and the program data are transferred to one of the bit lines BLe1, BLo1 through the sensing node SO1.
During the read operation or the program operation, the bit line select circuit 31 and the register circuit 32 have the same operation as the bit line select circuit 21 and the register circuit 22. Read data from one of the bit lines BLe2, BLo2 are transferred to the register circuit 32 through the sensing node SO2. Program data, which will be programmed into a memory cell, is connected to one of the bit lines BLe2, BLo2 through the sensing node SO2. As a result, at the time of the read operation or the program operation, the sensing nodes SO1, SO2 have voltage levels, each corresponding to read data or program data. At this time, the voltages of the sensing nodes SO1, SO2 may be changed due to coupling capacitance component (Cc) between the sensing nodes SO1, SO2.
As a result, a problem arises because erroneous read data or program data may be generated. This problem can be more profound when a flash memory device is highly integrated and the number of bit lines increases. As the distance between the sensing nodes becomes more narrow, the voltage of the sensing node has greater influence on the voltage of a neighboring sensing node. In addition, the page buffer circuit 11 includes page buffers, each connected to a pair of bit lines. As a result, a problem arises because the overall chip size increases since the number of page buffers increases when the number of bit lines increases.